The invention relates to the field of memory cells of the SRAM type.
A memory cell of the SRAM type generally include several CMOS storage transistors connected to one another while forming a bistable element made up of two inverters mounted head-to-tail (the output of the first inverter is connected to the input of the second inverter, and the output of the second inverter is connected to the input of the first inverter) and making it possible to store a bit.
Document [1] “Stable SRAM Cell Design for the 32 nm Node and Beyond” by L. Chang et al., Proc. Of Symposium on VLSI Technology, 2005, describes a memory cell of the SRAM type including eight CMOS transistors. Four of the eight CMOS transistors form the bistable element, two others of the eight CMOS transistors correspond to write access transistors and form a write port of the memory cell, and the last two CMOS transistors correspond to read access transistors and form a read port of the memory cell. A first of the two CMOS transistors of the read port includes its gate connected to the input of one of the two inverters of the bistable elements, its source connected to a reference potential, and its drain connected to the source of the second of the two CMOS transistors of the read port. The second of the two CMOS transistors of the read port includes its drain connected to a read bit line (on which a power supply potential VDD is applied prior to a read operation so that a current can flow through the two CMOS transistors of the read port during a read operation of the stored bit) and its gate connected to a read word line that makes it possible to command the beginning of the read operation via the application of a read command signal on that gate.
Such a read port nevertheless has the drawbacks of having significant leak currents, and does not make it possible to interleave bits between several interconnected memory cells. Furthermore, the electricity consumption of such a memory cell is high.
In order to reduce the electricity consumption of this type of memory cell, several documents propose using transistors of the TFET (Tunnel Field-Effect Transistor) type instead of CMOS transistors to produce memory cells of the SRAM type.
Document [2] “Low-Power Circuit Analysis and Design Based on Heterojunction Tunneling Transistors (HETTs)” by Y. Lee et al., Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 21, no. 9, pp. 1632-1643, Sep. 9, 2013, describes the production of a memory cell of the SRAM type including four TFET transistors (two of type n and two of type p) with heterojunctions forming a bistable element. Two other TFET access transistors of type n are coupled to the bistable element, each including its drain connected to the input of one of the two inverters of the bistable element, and form the write port of the memory cell. Another TFET transistor of type n is used to form a read port separate from the write port.
However, such a memory cell has several drawbacks:                low noise margins;        significant leak currents at the write port and the read port;        no possible interleaving of bits between several interconnected memory cells;        limited current through the TFET transistor of the read port.        
Document [3] “A Comparative Analysis of Tunneling FET Circuit Switching Characteristics and SRAM Stability and Performance” by Y.-N Chen et al., Proc. Of European Solid State Devices Conference (ESSDERC), 2012, describes a memory cell of the SRAM type close to that described in document [2], but the read port of which is formed by two TFET transistors of type n. A first of the two TFET transistors of the read port includes its gate connected to the input of one of the two inverters of the bistable element, its source connected to an electric reference potential, and its drain connected to the source of the second of the two TFET transistors of the read port. The second of the two TFET transistors of the read port has its drain connected to the read bit line and its gate connected to the read word line.
Such a memory cell also has several drawbacks, in particular:                no possible interleaving of bits;        limited read speed due to the two TFET transistors of the read port that are positioned along the discharge path of the read current from the read bit line to the reference electric potential.        